AT2k Design BBS Message Area
Casually read the BBS message area using an easy to use interface. Messages are categorized exactly like they are on the BBS. You may post new messages or reply to existing messages!

You are not logged in. Login here for full access privileges.

Previous Message | Next Message | Back to Slashdot  <--  <--- Return to Home Page
   Local Database  Slashdot   [97 / 100] RSS
 From   To   Subject   Date/Time 
Message   VRSS    All   Intel's Make-Or-Break 18A Process Node Debuts For Data Center Wi   March 4, 2026
 10:20 AM  

Feed: Slashdot
Feed Link: https://slashdot.org/
---

Title: Intel's Make-Or-Break 18A Process Node Debuts For Data Center With 288-
Core Xeon 6+ CPU

Link: https://hardware.slashdot.org/story/26/03/04/...

Intel has formally unveiled its Xeon 6+ "Clearwater Forest" data-center
processor with up to 288 cores, built on the company's new Intel 18A process
and using Foveros Direct packaging. The chip targets telecom, cloud, and edge-
AI workloads with massive parallelism, large caches, and high-bandwidth DDR5-
8000 memory. Tom's Hardware reports: Intel's Xeon 6+ processors with up to
288 cores combine 12 compute chiplets containing 24 energy-efficient Darkmont
cores per tile that are produced using 18A manufacturing technology, two I/O
tiles made on Intel 7 production node, as well as three active base tiles
made on Intel 3 fabrication process. The compute tiles are stacked on top of
the base dies using Intel's Foveros Direct 3D technology, whereas lateral
connections are enabled by Intel's EMIB bridges. Intel's 'Darkmont'
efficiency cores have received rather meaningful microarchitectural upgrades.
Each core integrates a 64 KB L1 instruction cache, a broader fetch and decode
pipeline, and a deeper out-of-order engine capable of tracking more in-flight
operations. The number of execution ports has also been increased in a bid to
improve both scalar and vector throughput under heavily threaded server
workloads. From a cache hierarchy standpoint, the design groups cores into
four-core blocks that share approximately 4 MB of L2 cache per block. As a
result, the aggregate last-level cache across the full package surpasses 1
GB, roughly 1,152 MB in total. This unusually large pool is intended to keep
data close to hundreds of active cores and reduce dependence on external
memory bandwidth, which in turn is meant to both increase performance and
lower power consumption. Platform-wise, the processor remains drop-in
compatible with the current Xeon server socket, so the CPU has 12 memory
channels that support DDR5-8000, 96 PCIe 5.0 lanes with 64 lanes supporting
CXL 2.0.

Read more of this story at Slashdot.

---
VRSS v2.1.180528
  Show ANSI Codes | Hide BBCodes | Show Color Codes | Hide Encoding | Hide HTML Tags | Show Routing
Previous Message | Next Message | Back to Slashdot  <--  <--- Return to Home Page

VADV-PHP
Execution Time: 0.0155 seconds

If you experience any problems with this website or need help, contact the webmaster.
VADV-PHP Copyright © 2002-2026 Steve Winn, Aspect Technologies. All Rights Reserved.
Virtual Advanced Copyright © 1995-1997 Roland De Graaf.
v2.1.250224